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1 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges 2003 integrated device technology, inc. dsc-6201/14 c idtcspt857c commercial and industrial temperature ranges 2.5v - 2.6v phase locked loop differential 1:10 sdram clock driver june 2003 the idt logo is a registered trademark of integrated device technology, inc. features: ? 1 to 10 differential clock distribution ? optimized for clock distribution in ddr (double data rate) sdram applications ? operating frequency: 60mhz to 220mhz ? very low skew: ? <100ps for pc1600 - pc2700 ? <75ps for pc3200 ? very low jitter: ? <75ps for pc1600 - pc2700 ? <50ps for pc3200 ? 2.5v av dd and 2.5v v ddq for pc1600-pc2700 ? 2.6v av dd and 2.6v v ddq for pc3200 ? cmos control signal input ? test mode enables buffers while disabling pll ? low current power-down mode ? tolerant of spread spectrum input clock ? available in 48-pin tssop, 40-pin vfqfpn, and 56-pin vfbga packages description: the cspt857c is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y [0:9] , y [0:9] ) and one differential pair of feedback clock output (fbout, fbout ). external feedback pins (fbin, fbin ) for synchronization of the outputs to the input reference is provided. a cmos enable/disable pin is available for low power disable. when the input frequency falls below approximately 20mhz, the device will enter power down mode. in this mode, the receivers are disabled, the pll is turned off, and the output clock drivers are tristated, resulting in a current consumption of less than 200 a. the cspt857c requires no external components and has been optimised for very low i/o phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. the cspt857c, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. the cspt857c is available in commercial temperature range (0 c to +70 c) and industrial temperature range (-40 c to +85 c). see ordering information for details. applications: ? meets or exceeds jedec standard jesd 82-1a for registered ddr clock driver ? meets proposed ddr1-400 specification ? for all ddr1 speeds: pc1600 (ddr200), pc2100 (ddr266), pc2700 (ddr333), pc3200 (ddr400) ? along with sstv16857, sstvf16857, sstv16859, sstvm16859, sstvf16859, ddr1 register, provides complete solution for ddr1 dimms
2 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver y0 y0 fbout y1 y1 y5 y5 y4 y4 y3 y3 y2 y2 y8 y8 y6 y6 y7 y7 y9 y9 fbout pll clk pwrdwn clk fbin fbin test mode logic av dd functional block diagram
3 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges pin configurations 56 ball vfbga package layout abc e f g h j k d 6 5 4 3 2 1 y 7 v ddq pwr dwn fbin fbout y 6 gnd y 7 v ddq gnd fbin fbout y 5 y 6 y 5 gnd y 8 y 9 y 9 y 8 y 0 y 0 y 1 y 1 y 2 y 4 y 3 y 2 v ddq gnd gnd gnd v ddq v ddq gnd v ddq gnd gnd v ddq v ddq clk clk av dd v ddq gnd agnd y 4 y 3 nc nc nc nc nc nc nc nc vfbga top view 0.65mm top view a b c d e f g h j k a b c d e f g h j k 1 2 3 4 5 6 1 3 2 4 5 6
4 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver v ddq gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 32 31 30 29 1 v ddq v ddq gnd 25 26 27 28 gnd y 5 y 5 gnd y 0 y 0 y 1 y 1 gnd y 2 y 2 clk clk av dd y 3 y 3 v ddq y 4 y 6 y 6 gnd y 7 y 7 pwrdwn fbin fbin v ddq fbout fbout y 8 y 8 v ddq y 9 y 9 gnd gnd gnd y 4 gnd v ddq v ddq v ddq agnd pin configurations tssop top view vfqfpn top view gnd y 2 y 2 v ddq clk clk v ddq av dd agnd gnd y 3 y 3 v d d q y 4 y 4 y 9 y 9 v d d q y 8 y 8 y 7 y 7 v ddq pwrdwn fbin fbin v ddq v ddq fbout fbout y 1 y 1 v d d q y 0 y 0 y 5 y 5 v d d q y 6 y 6 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 absolute maximum ratings (1) symbol rating max unit v ddq , av dd supply voltage range ?0.5 to +3.6 v v i (2) input voltage range ?0.5 to v ddq + 0.5 v v o (2) voltage range applied to any ?0.5 to v ddq + 0.5 v output in the high or low state i ik input clamp current ?50 ma (v i <0) i ok output clamp current 50 ma (v o <0 or v o > v ddq ) i o continuous output current 50 ma (v o =0 to v ddq ) v ddq or gnd continuous current 100 ma tstg storage temperature range ? 65 to +150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. capacitance (1) parameter description min. typ. max. unit c in input capacitance 2.5 ? 3.5 pf v i = v ddq or gnd c i( ? ) delta input capacitance -0.25 ? 0.25 pf v i = v ddq or gnd c l load capacitance ? 14 ? pf note: 1. unused inputs must be held high or low to prevent them from floating.
5 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges pin description (tssop/tvsop) pin name pin number description agnd 17 ground for analog supply av dd 16 analog supply clk, clk 13, 14 differential clock input fbin , fbin 35, 36 feedback differential clock input fbout, fbout 32, 33 feedback differential clock output gnd 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 ground pwrdwn 37 output enable for y and y v ddq 4, 11, 12, 15, 21, 28, 34, 38, 45 i/o supply y [0:9] 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 buffered output of input clock, clk y [0:9] 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 buffered output of input clock, clk pin description (vfbga) pin name pin number description agnd h1 ground for analog supply av dd g2 analog supply clk, clk f1, f2 differential clock input fbin , fbin f5, f6 feedback differential clock input fbout, fbout h6, g5 feedback differential clock output gnd a3, a4, c1, c2, c5, c6, h2, h5, k3, k4 ground pwrdwn e6 output enable for y and y v ddq b3, b4, e1, e2, e5, g1, g6, j3, j4 i/o supply y [0:9] a1, a6, b2, b5, d1, d6, j2, j5, k1, k6 buffered output of input clock, clk y [0:9] a2, a5, b1, b6, d2, d5, j1, j6, k2, k5 buffered output of input clock, clk recommended operating conditions symbol parameter min. typ. max. unit av dd supply voltage v ddq ? 0.12 v ddq 2.7 v v ddq i/o supply voltage pc1600-pc2700 2.3 2.5 2.7 v pc3200 2.5 2.6 2.7 t a operating free-air temperature -40 ? +85 c pin description (mlf) pin name pin number description agnd 9 ground for analog supply av dd 8 analog supply clk, clk 5, 6 differential clock input fbin , fbin 25, 26 feedback differential clock input fbout, fbout 21, 22 feedback differential clock output gnd 1, 10 ground pwrdwn 27 output enable for y and y v ddq 4, 7, 13, 18, 23, 24, 28, 33, 38 i/o supply y [0:9] 3, 12, 14, 17, 19, 29, 32, 34, 37, 39 buffered output of input clock, clk y [0:9] 2, 11, 15, 16, 20, 30, 31, 35, 36, 40 buffered output of input clock, clk
6 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver notes: 1. h = high voltage level l = low voltage level z = high-impedance off-state x = don't care 2. av dd nominal is 2.5v for pc1600, pc2100, and pc2700. av dd nominal is 2.6v for pc3200. 3. additional feature that senses when the clock input is less than approximately 20mhz and places the part in sleep mode. reci ever inputs and pll are turned off and outputs = tristate. function table (1) inputs outputs av dd pwrdwn clk clk y y fbout fbout pll gnd h l h l h l h bypassed/off gnd h h l h l h l bypassed/off x l l h z z z z off x l h l z z z z off nominal (2) hlhlhl h on nominal (2) hh lhlh l on nominal (2,3) x <20mhz <20mhz z z z z off dc electrical characteristics over operating range for pc1600 - pc2700 following conditions apply unless otherwise specified: commercial: t a = 0c to +70c; industrial: t a = -40c to +85c symbol parameter conditions min. typ. max. unit v ik input clamp voltage (all inputs) v ddq = 2.3v, i i = -18ma ?? ? 1.2 v v il (dc) static input low voltage pwrdwn ? 0.3 ? 0.7 v v ih (dc) static input high voltage pwrdwn 1.7 ? v ddq + 0.3 v il (ac) dynamic input low voltage clk, clk , fbin, fbin ?? 0.7 v v ih (ac) dynamic input high voltage clk, clk , fbin, fbin 1.7 v ddq v ol output low voltage a vdd /v ddq = min., i ol = 100 a ? 0.1 v a vdd /v ddq = min., i ol = 12ma ? 0.6 v oh output high voltage a vdd /v ddq = min., i oh = -100 av ddq ? 0.1 v a vdd /v ddq = min., i oh = -12ma 1.7 v ix input differential cross voltage v ddq /2 ? 0.2 v ddq /2 + 0.2 v v id(dc) (1) dc input differential voltage 0.36 v ddq + 0.6 v v id(ac) (1) ac input differential voltage 0.7 v ddq + 0.6 v i in input current v ddq = 2.7v, v i = 0v to 2.7v 10 a i ddpd power-down current on v ddq and a vdd a vdd /v ddq = max., clk = 0mhz or pwrdwn = l ? 100 200 a i ddq dynamic power supply current on v ddq a vdd /v ddq = max., clk = 200mhz, 120 ? /14pf ? 320 360 ma a vdd /v ddq = max., clk = 170mhz, 120 ? /14pf ? 250 300 i add dynamic power supply current on a vdd a vdd /v ddq = max., clk = 170mhz ? 12 m a note: 1. v id is the magnitude of the difference between the input level on clk and the input level on clk .
7 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges dc electrical characteristics over operating range for pc3200 following conditions apply unless otherwise specified: commercial: t a = 0c to +70c; industrial: t a = -40c to +85c symbol parameter conditions min. typ. max. unit v ik input clamp voltage (all inputs) v ddq = 2.5v, i i = -18ma ?? ? 1.2 v v il (dc) static input low voltage pwrdwn ? 0.3 ? 0.7 v v ih (dc) static input high voltage pwrdwn 1.7 ? v ddq + 0.3 v il (ac) dynamic input low voltage clk, clk , fbin, fbin ?? 0.7 v v ih (ac) dynamic input high voltage clk, clk , fbin, fbin 1.7 v ddq v ol output low voltage a vdd /v ddq = min., i ol = 100 a ? 0.1 v a vdd /v ddq = min., i ol = 12ma ? 0.6 v oh output high voltage a vdd /v ddq = min., i oh = -100 av ddq ? 0.1 v a vdd /v ddq = min., i oh = -12ma 1.7 v ix input differential cross voltage v ddq /2 ? 0.2 v ddq /2 + 0.2 v v id(dc) (1) dc input differential voltage 0.36 v ddq + 0.6 v v id(ac) (1) ac input differential voltage 0.7 v ddq + 0.6 v i in input current v ddq = 2.7v, v i = 0v to 2.7v 10 a i ddpd power-down current on v ddq and a vdd a vdd /v ddq = max., clk = 0mhz or pwrdwn = l ? 100 200 a i ddq dynamic power supply current on v ddq a vdd /v ddq = max., clk = 200mhz, 120 ? /14pf ? 320 360 ma a vdd /v ddq = max., clk = 200mhz, 120 ? /14pf ? 250 300 i add dynamic power supply current on a vdd a vdd /v ddq = max., clk = 200mhz ? 12 m a note: 1. v id is the magnitude of the difference between the input level on clk and the input level on clk . timing requirements for pc3200 symbol parameter min. max. unit f clk operating clock frequency (1,2) 60 220 m h z application clock frequency (1,3) 60 220 m h z t dc input clock duty cycle 40 60 % t l stabilization time (4) ? 100 s notes: 1. the pll will track a spread spectrum clock input. 2. operating clock frequency is the range over which the pll will lock, but may not meet all timing specifications. 3. application clock frequency is the range over which timing specifications apply. 4. stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its ref erence signal after power up. timing requirements for pc1600 - pc2700 symbol parameter min. max. unit f clk operating clock frequency (1,2) 60 200 m h z application clock frequency (1,3) 60 200 m h z t dc input clock duty cycle 40 60 % t l stabilization time (4) ? 100 s notes: 1. the pll will track a spread spectrum clock input. 2. operating clock frequency is the range over which the pll will lock, but may not meet all timing specifications. 3. application clock frequency is the range over which timing specifications apply. 4. stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its ref erence signal after power up.
8 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver switching characteristics for pc1600 - pc2700 symbol description test conditions min. typ. (1) max. unit t plh (1) low to high level propagation delay time test mode, clk to any output 4.5 ns t phl (1) high to low level propagation delay time test mode, clk to any output 4.5 ns t jit(per) jitter (period), see figure 6 66mhz ? 90 90 ps 100/ 133/ 167/ 200 mhz ? 75 75 t jit(cc) jitter (cycle-to-cycle), see figure 3 66mhz ? 180 180 ps 100/ 133/ 167/ 200 mhz ? 75 75 t jit(hper) half-period jitter, see figure 7 66mhz ? 160 160 ps 100/ 133/ 167/ 200 mhz ? 100 100 t slr(o) output clock slew rate (single-ended) 100/ 133/ 167/ 200 mhz (20% to 80%) 1 2.5 v/ns t slr(i) input clock slew rate 1 4 v/ns t ( ? ) static phase offset, see figure 4 (2,3) 66/ 100/ 133/ 167/ 200 mhz ? 50 50 ps t sk(o) output skew, see figure 5 75 ps t r, t f output rise and fall times (20% to 80%) load: 120 ? / 14pf 650 900 ps v ox (5) output differential voltage differential outputs are terminated v ddq /2 v ddq /2 v with 120 ? ? 0.15 + 0.15 the pll on the cspt857 will meet all the above test parameters while supporting ssc synthesizers (4) with the following parameters: ssc modulation frequency ? 30 ? 50 khz ssc clock input frequency deviation ? 0 ? -0.5 % f 3db pll loop bandwidth ?? 5 ? mhz notes: 1. refers to transition of non-inverting output. 2. static phase offset does not include jitter. 3. t( ) is measured with input clock slew rate t slr ( i ) = 2v/ns and an input differential voltage v id of 1.75v. 4. the ssc requirements meet the intel pc100 sdram registered dimm specification. 5. v ox is specified at the sdram clock input or test load.
9 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges switching characteristics for pc3200 symbol description test conditions min. typ. (1) max. unit t plh (1) low to high level propagation delay time test mode, clk to any output 4.5 ns t phl (1) high to low level propagation delay time test mode, clk to any output 4.5 ns t jit(per) jitter (period), see figure 6 66mhz ? 90 90 ps 200 mhz ? 50 50 t jit(cc) jitter (cycle-to-cycle), see figure 3 66mhz ? 180 180 ps 200 mhz ? 75 75 t jit(hper) half-period jitter, see figure 7 66mhz ? 160 160 ps 200 mhz ? 75 75 t slr(o) output clock slew rate (single-ended) 200 mhz (20% to 80%) 1 2.5 v/ns t slr(i) input clock slew rate 1 4 v/ns t ( ? ) static phase offset, see figure 4 (2,3) 200 mhz ? 50 50 ps t sk(o) output skew, see figure 5 75 ps t r, t f output rise and fall times (20% to 80%) load: 120 ? / 14pf 650 900 ps v ox (5) output differential voltage differential outputs are terminated v ddq /2 v ddq /2 v with 120 ? ? 0.15 + 0.15 the pll on the cspt857 will meet all the above test parameters while supporting ssc synthesizers (4) with the following parameters: ssc modulation frequency ? 30 ? 50 khz ssc clock input frequency deviation ? 0 ? -0.5 % f 3db pll loop bandwidth ?? 5 ? mhz notes: 1. refers to transition of non-inverting output. 2. static phase offset does not include jitter. 3. t( ) is measured with input clock slew rate t slr ( i ) = 2v/ns and an input differential voltage v id of 1.75v. 4. the ssc requirements meet the intel pc100 sdram registered dimm specification. 5. v ox is specified at the sdram clock input or test load.
10 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver test circuit and switching waveforms figure 1. output load v dd cspt857c v ss r = 120 ? z = 60 ? z = 60 ? c = 14pf c = 14pf v ss v ss v ddq /2 v ddq /2 r = 10 ? z = 60 ? z = 60 ? c = 14pf c = 14pf z = 50 ? z = 50 ? r = 50 ? r = 50 ? 0v 0v r = 10 ? scope cspt857c v ddq /2 v ddq /2 figure 2. output load test circuit
11 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges yx, fbout t jit(cc) t cycle n t cycle n+1 = yx, fbout t cycle n t cycle n+1 fbin clk t (?)n t (?)n + 1 t (?) = n n = n 1 t (?)n clk fbin (n is a large number of samples) figure 3. cycle-to-cycle jitter figure 4. static phase offset yx, fbout yx t sk(o) yx, fbout yx figure 5. output skew test circuit and switching waveforms
12 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver yx, fbout yx, fbout t jit(per) = t cycle n 1 f o yx, fbout yx, fbout t cycle n 1 f o yx, fbout yx, fbout 1 f o t jit(hper) = t half period n 1 2*f o yx, fbout yx, fbout t half period n t half period n+1 figure 6. period jitter figure 7. half-period jitter test circuit and switching waveforms
13 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges figure 8. input and output slew rates clock inputs and outputs 80% 20% v id , v od t r t f 80% 20% application information clock loading on the pll outputs (pf) clock structure # of sdram loads per clock min. max. #1 2 4 7 #2 4 8 14 test circuit and switching waveforms
14 commercial and industrial temperature ranges idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver application information cspt857c c = 14pf r = 120 ? fbin fbin c = 14pf r = 120 ? clk clk feedback path r = 120 ? z = 60 ? z = 60 ? 8 more sdram sdram ~2.5" ~0.3" ~0.6" (split to terminator) (1) cspt857c c = 14pf r = 120 ? fbin fbin c = 14pf r = 120 ? clk clk feedback path r = 120 ? z = 60 ? z = 60 ? 8 more sdram sdram ~2.5" ~0.3" ~0.6" (split to terminator) sdram sdram stacked stacked (1) figure 9. clock structure 1 figure 10. clock structure 2 note: 1. memory module vendors may need to adjust the feedback capacitive load in order to meet ddr sdram registered dimm timing requi rements.
15 idtcspt857c 2.5v - 2.6v pll differential 1:10 sdram clock driver commercial and industrial temperature ranges ordering information idtcspt xxxxx xx package device type 857c pa pag bv nl nlg thin shrink small outline package tssop - green very fine pitch ball grid array thermally-enhanced plastic very fine pitch flat no lead package mlf - green 2.5v - 2.6v pll differential 1:10 sdram clock driver process blank i 0c to +70c (commercial) -40c to +85c (industrial) x corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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